Semiconductor component manufacturers are constantly striving to increase the speed of their components. Because a semiconductor component, such as a microprocessor, contains up to a billion transistors or devices, the focus for increasing speed has been to decrease gate delays of the semiconductor devices that make up the semiconductor component. As a result, the gate delays have been decreased to the point that speed is now primarily limited by the propagation delay of the metallization system used to interconnect the semiconductor devices with each other and with elements external to the semiconductor component. Metallization systems are typically comprised of a plurality of interconnect layers vertically separated from each other by a dielectric material and electrically coupled to each other by metal-filled vias or conductive plugs. Each layer contains metal lines, metal-filled vias, or combinations thereof separated by an insulating material. FIG. 1 is a top view of a portion of a prior art metallization system 12 formed in a semiconductor component 10. Metallization system 12 includes a continuous or gap-free input interconnect 14 coupled to a continuous or gap-free output interconnect 16 by a routing interconnect 18. Routing interconnect 18 is a portion of an interconnect layer in a plane either above or below the plane in which input and output interconnects 14 and 16, respectively, are formed. One end of routing interconnect 18 is coupled to a corresponding end of input interconnect 14 by a metal filled via 20 and an opposing end of routing interconnect 18 is coupled to a corresponding end of output interconnect 16 by a metal filled via 22. The width W1 of input and output interconnects 14 and 16, respectively, is much larger than the width W2 of routing interconnect 18. When used for signal transmission, current flows from input interconnect 14 through routing interconnect 18 then through output interconnect 16.
Metallization system 12 is also suitable for use as an electromigration test structure. Because the widths of input and output interconnects 14 and 16, respectively, are greater than the width of routing interconnect 18, the current density in routing interconnect 18 is greater than the current density in interconnects 14 and 16. Thus, electromigration failures occur in routing interconnect 18 rather than in interconnects 14 and 16. Although useful for electromigration analysis, when metallization system 12 is used as either a signal transmission structure or a test structure, the large widths of the input and output interconnects induces the formation of stress voids in these portions of the metallization system. The stress voids tend to collect near vias, resulting in increased interconnect resistance, formation of open circuits, decreased yield, and decreased reliability.
Accordingly, what is needed is a metallization system that inhibits the formation of stress induced voids, a method for precluding stress induced void formation in a semiconductor component, and a method for manufacturing a semiconductor component that includes a stress-induced void-preclusion feature.